1. Field of the Invention
This invention relates to a semiconductor memory device. For example, this invention relates to a nonvolatile semiconductor memory with MOS transistors each having a floating gate and a control gate.
2. Description of the Related Art
Conventionally, NOR and NAND flash memories are known and widely used as nonvolatile semiconductor memory devices.
In recent years, a flash memory combining the features of the NOR flash memory and the NAND flash memory has been proposed. Hereinafter, such a type of flash memory is referred to as a 2Tr flash memory. A proposal relating to the 2Tr flash memory has been made in, for example, Wei-Hua Liu, “A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-only Application,” Non-Volatile Semiconductor Memory Workshop 4,1, 1997. Each memory cell of the 2Tr flash memory has two MOS transistors. One MOS transistor functions as a nonvolatile memory section. In addition, this MOS transistor comprises a control gate and a floating gate, and is connected to a bit line. The other MOS transistor is connected to a source line, and is used to select a memory cell.
In the flash memory, shunt wirings are used in order to apply a potential to a word line or a source line at a high speed. The shunt wires are each connected to the word line or the source line in an exclusive region (shunt region) provided in a memory cell array. Therefore, in the shunt region, the regularity of the memory cell arrays is distorted. Also in an edge of a memory cell array, the regularity is distorted. Thus, there has been a problem that a fault is very likely to occur with the word line or bit line which is adjacent to the edge of the memory cell array or shunt region, and, even if an error checking and correcting (ECC) circuit is used, it is difficult to recover a memory cell.